JTAG: TCK, TMS, TDI and TDO

Applies to: Single-target signal diagram. Pin order, voltage and optional reset signals depend on the exact probe and connector.

When to use it

Using supported programming, debugging or boundary-scan tools with documented target hardware.

Why it works this way

Separate clock, state control and serial input/output let a probe communicate with a target's test-access port.

Connection reference

Make the connection

1. Match the target connector and I/O voltage; identify optional nTRST and system reset separately.
2. For multiple targets, use the documented chain order and instruction-register configuration.

Check before powering

• Do not assume that a similarly sized header is JTAG.
• Do not connect a probe's power-output contact unless the board and probe documentation explicitly allow it.

Sources & review

Source documents inspected; independent electrical and bench review pending. Reviewed 2026-09-27.

• SEGGER: J-Link interface description
  20-pin JTAG signal direction and VTref · checked 2026-09-27

Original writing and diagram by Kal / Valleytech Solutions, CC BY 4.0. Manufacturer artwork and documentation retain their own rights. CC BY 4.0

Continue learning

• SWD: connect a Cortex debug probe

Open this guide in the app · All wiring guides